This invention relates to an information storage device and, more particularly, to an active electronic memory cell of the type having a pair of transistors cross-coupled to form a flip-flop.
Various types of flip-flop memory cells are well known in the art, most utilizing at least six transistors. For example, as described in U.S. Pat. No. 3,815,106 to Wiedmann and U.S. Pat. No. 4,081,697 to Nakano, a memory cell typically includes a pair of cross-coupled NPN transistors with a pair of PNP transistors acting as loads for the NPN flip-flop transistors. A second pair of PNP transistors is then used to couple the flip-flop cell to the bit lines. Although such arrangements are highly useful, it would be desirable to decrease the cell size, increase operating speed and decrease the power requirements of such memory cells.
The quest for a higher performance memory device has led to development of the transistor gated PNP load (TGPL) memory cell shown in FIG. 1 which utilizes only four transistors. This cell utilizes cross-coupled NPN transistors 10 and 12 and a pair of PNP load transistors 14 and 16. In order to read the contents of the cell, a low potential read signal is supplied to line 18 to turn on both of transistors 14 and 16. Alternatively, line 18 could be maintained at a constant potential and a positive pulse applied to the emitters of transistors 14 and 16. Assuming that a "1" is stored in the cell and the NPN transistor 10 is on and transistor 12 is off, the potential at the collector of transistor 10 and base of transistor 12 will be lower than that at the collector of transistor 12 and base of transistor 10. When the two transistors 14 and 16 are simultaneously turned on, this imbalance will show up as a potential difference between the emitters of transistors 10 and 12 which are coupled to bit lines 20 and 22, respectively, and a sense amplifier will determine the contents of the memory cell by detecting this potential difference.
Although the cell illustrated in FIG. 1 achieves improvements in both cell size and performance over prior art cells taught in the above-mentioned U.S. patents, it would still be desirable to achieve further improvements in these same areas.
In further attempts to achieve a higher performance memory cell, the cell shown in FIG. 2 has been devised. The cell of FIG. 2 is known as a complementary transistor switch (CTS) memory cell in which PNP and NPN devices simultaneously drive and act as a load for one another. The PNP transistor 30 will drive NPN transistors 34 and 36, and these transistors 34 and 36 will also act as a load for the transistor 30 through Schottky barrier diode (SBD) 42. Similarly, the transistor 32 will drive transistors 38 and 40 which, in turn, will act as a load for the transistor 32 through the SBD 44. Since the levels within the cell are established entirely by junction voltages rather than linear IR drops, the cell will operate satisfactorily at low current levels, and the use of SBD's 42 and 44 for "on-off" level definition has the further benefit of preventing saturation. Also, the use of a PNP to drive the base of an NPN transistor results in minimal frequency requirements for the PNP and encourages the use of a lateral PNP/vertical NPN as an integrated device.
In the typical operation of the cell of FIG. 2, a "0" is defined by the conduction of transistors 30 and 36, which also establish internal bias such that transistors 32 and 38 are substantially non-conducting and define a "1". Assuming such a memory state, i.e. transistors 30 and 36 conducting, application of a word select signal will result in conduction of this signal to the base of transistor 36 through transistor 30, thus increasing the conduction of the left side of the cell. This high potential at the base of transistor 36 will also be supplied to the base of PNP transistor 32, thus further decreasing the conduction of the right side of the cell. Reading is accomplished by differentially sensing the diodes 42 and 44 with transistors 48 and 50, i.e. if the left side of the cell is conducting, the potential at the base of PNP transistor 30 will be low, thus resulting in non-conduction of NPN transistor 48, while the relatively higher potential at the base of PNP transistor 32 will result in conduction of NPN transistor 50.
In order to change the state of the cell, the off side, or non-conducting side, of the cell is caused to conduct by the application of a negative pulse to the emitter of transistor 40. This will cause conduction of transistor 40 and a consequent lowering of the base potentials of PNP transistor 32 and NPN transistor 36, thereby causing the right-side to conduct while the left-side becomes non-conducting.
Further details of the CTS memory cell can be had by referring to "Complementary Transistor Switch Memory Cell", by J. A. Dorler et al., IBM Technical Disclosure Bulletin, Vol. 16, No. 12, May 1974, pages 3931-3932, and "Lateral PNP Design For Memory Cell", by J. A. Dorler et al., IBM Technical Disclosure Bulletin, Vol. 17, No. 6, Nov. 1974, pages 1619-1620.
A problem with the cell structure of FIG. 2 is that, since the reading of the cell is accomplished by differentially sensing the diodes 42 and 44, and since the potentials across these diodes define a very delicate imbalance in the cell, additional transistors 48 and 50 are required as buffers to connect the cell to the bit lines. Further, in conventional fabrication techniques, npn junction transistors are fabricated vertically, i.e., with a buried collector or subcollector, and pnp transistors are then fabricated horizontally with the n-type subcollector region serving as an npn collector and pnp base. This permits pnp-npn transistor combinations to be fabricated in a merged structure which decreases the size requirements for each cell. Transistors 48 and 50, however, have their collectors typically coupled to a voltage source and, since none of the collectors of transistors 34-40 are coupled to the same source, transistors 48 and 50 will require a separate isolation region. This results in an undesirable increase in the layout area required for each cell.